In multi-ported internally cached dynamically random accessed memory systems (AMPIC/DRAM) of the type described in said copending application and hereinafter more fully explained, independent serial interfaces buffer cache data written into the AMPIC device before writing it into shared internal DRAM banks, over which contention arises. The buffer slot caching of the data received on the serial interfaces reduces the chances that internal contention to a particular DRAM bank will affect the overall external performance of the serial interfaces by increasing the number of requests that may be outstanding to a particular internal AMPIC DRAM bank before it becomes necessary to stop the writing of information on one of the external serial interfaces in order to avoid overrunning the limited write cache buffer slot space for that particular serial interface. Because of the potential for a large number of read and write access requests to be contending for switching to a particular DRAM bank, the time it takes the AMPIC device to write data into one of the internal DRAM banks can significantly vary up to some finite maximum amount of time.
More generally, the technique of said co-pending application as used in a system having a master controller such as a central processing unit (CPU) having parallel data ports and a dynamic random access memory (DRAM) each connected to and competing for access to a common system bus interface, resides in an improved DRAM architecture comprising the multi-port internally cached DRAM (AMPIC DRAM) wherein a plurality of independent serial data interfaces is provided, each connected between a separate external I/O resource and internal DRAM memory through corresponding buffers. Switching is effected between the serial interfaces and the buffers, under a dynamic logic control by the bus master controller, such as said CPU, for switching allocation as appropriate for the desired data routability amongst the I/O resources addressed destinations. Arbitration is performed for bus interface access amongst the various active packet buffers and the CPU, but with no arbitration required to receive or transmit data from or to the packet buffers via the serial interfaces. The AMPIC DRAM switching module, furthermore, assigns any buffer to any serial interface and without any intermediate step of transferring data between the buffer and the core DRAM, and with each buffer having the capability to interface with up to all the serial interfaces simultaneously when defined as a port, each buffer, moreover, being configured for the same port size as the port to which it is connected or docked.
This technique is useful for handling with relatively large and short data messages and with reduced bus contention
While reducing arbitration requirements of bus access contention for relatively large messages through efficient utilization of the data port cache slots and DRAM bank access randomization as much as possible, in accommodating for relatively short or small messages, the AMPIC DRAM array system may, however, under-utilize the available space in a buffer cache slot, resulting in a rapid depletion of available buffer slots.
It is accordingly to the improvement of such small message slot space under-utilization that the present invention is primarily, though not exclusively concerned--such being of particular concern with ATM and similar type system operations. The present invention accomplishes this through eliminating the need for external control and addresses storage, using rather, inherent data header destination information, and, in so doing, reducing to zero all bus contention for DRAM access, as well, as will be more fully explained.